====== GNU 'make' Notes ======

\\
:!: Avoid appending a comment to a line with a variable declaration. Otherwise, some versions of ''make'' may consider the comment as part of the value string, which can yield strange effects.

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Here are some hints how to write a ''Makefile'' in a way that the project
is built quitely by default, but verbosely if required.

In **quiet mode** there's only a short info which command is being executed,
so build errors and warnings don't disappear in a noisy output.

In **verbose mode** the full commands are displayed, so it's possible to see exactly
which parameters are passed to each command.

<codedoc code>
# Define a variable V (verbose) which is 0 by default.
# Call 'make' with parameter "V=1" to get verbose output.
V ?= 0

# Define some helper variables depending on the value of V.
ifneq ("$(V)","0")
  # Verbose output.
  Q :=
  QM :=
  vecho = @true
else
  # Quiet output.
  Q := @
  QM := -s
  vecho = @echo
endif


# Override the builtin rules to compile a C module.
%.o: %.c
	$(vecho) "    $(CC)       $@"
	$(Q)$(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<


# Override the builtin rules to compile a C++ module.
%.o: %.cpp
	$(vecho) "    $(CXX)      $@"
	$(Q)$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c -o $@ $<


# Assume the default target is 'all', as usual, and the 
# real name of the target has been specified above, with
# a line 'TARGET = ...'
.PHONY: all
all: $(TARGET)


# Override the builtin rules to link the $(TARGET) binary.
$(TARGET): $(OBJS)
	$(vecho) "    Linking $@"
	$(Q)$(CC) -o $@ $(LDFLAGS) $^ $(LDLIBS)
</codedoc>


/*
Call a sub-make in a different directory:
<codedoc code>
	$(Q)$(MAKE) $(QM) -C mbgclock $@
</codedoc>
*/

----

 --- //Martin Burnicki [[martin.burnicki@burnicki.net]], last updated 2021-01-26//